Lithography processes are used to transfer patterns from a mask to a semiconductor device. As feature sizes on semiconductor devices decrease into the submicron range, there is a need for new lithography processes to pattern high-density semiconductor devices. Projection electron-beam lithography is a well-known reduction technique for patterning semiconductor devices. In general, a projection electron-beam lithography system scans a beam across a mask to create an image on the semiconductor device. Electron optics can be inserted to provide a means of image reduction. One particular type of projection electron beam lithography is known as Scattering with Angular Limitation in Projection Electron-Beam Lithography developed by Lucent Technologies, Incorporated of Murray Hill, New Jersey. The basic principles of this technique are illustrated in prior art FIG. 1.
From prior art FIG. 1, a mask 10 having a patterned scattering layer 14 is provided on membrane 12, through which an electron beam is projected as represented by the flux arrows 13. The patterned scattering layer 14 produces more electron scattering than the membrane 12 as a result of the difference in atomic numbers between the composition of the patterned scattering layer 14 and the membrane 12, i.e., the patterned scattering layer 14 has a higher atomic number than that of the membrane 12. The scattering effect 16 of the electron beam through portions of the mask 10 is illustrated in FIG. 1. As shown, those portions of the electron beam that pass through the patterned scattering layer 14 tend to be scattered through larger angles, as depicted by the scattering effect 16, when compared with those less scattered portions 17 that pass between unpatterned portions of the scattering layer 14.
As shown, the electron beam that passes through the mask 10 is focused through an electron focusing system represented by lens 20. The electron beam then passes through back focal plane filter 30 having an aperture 18 that is provided to permit passage of those portions of the electron beam that were not scattered by the patterned scattering layer 14 of the mask 10 through some finite angle. The electron beam is then projected onto a semiconductor wafer 40 having a plurality of die 42 and a resist layer 44 spun on the semiconductor wafer 40 by conventional techniques. The electron beam forms a high contrast image including areas of low intensity formed by those scattered portions 16 of the electron beam that pass through patterned portions of the mask 10, and areas of relatively high intensity formed by those less scattered portions 17 of the electron beam that pass through the unpatterned areas of the mask 10. In this way, a high-resolution image may be projected onto the resist layer 44, which is then developed to form an exposed resist layer. The patterned resist layer 44 may be used as an etch mask for the underlying material. It is noted that the electron optics of the system may be adjusted so as to provide a reduction in image size, typically 4X or one-fourth the image size on the mask 10.
A typical mask fabrication methodology using Scattering With Angular Limitation In Projection Electron-Beam Lithography is shown in prior art FIG. 2. FIG. 2 depicts cross-sectional views of processing steps applied to the same semiconductor wafer to form a mask. The methodology begins at step 50 by providing a silicon wafer 51, the silicon wafer having a silicon wafer top surface 53 and a silicon wafer bottom surface 52. At step 60, the silicon wafer 51 is processed to form a silicon nitride film 61 that is deposited around the silicon wafer 51, on both the top 53 and bottom 52 surfaces, using conventional low pressure chemical vapor deposition (LPCVD). The silicon nitride film 61 is typically called a membrane film, such as membrane 12 of FIG. 1, on which a scattering layer, such as the patterned scattering layer 14 of FIG. 1, will be formed. At step 70, two other films are deposited, using conventional sputtering techniques, to form an etch stop layer 72, such as a chromium layer, and a scatterer film 71, such as a tungsten layer, above the etch stop layer 72. The etch stop layer 72 is used to prevent an etch species, used during the patterning of the scatterer film 71, to "attack" the silicon nitride film 61. In step 80, a sacrificial layer 81, typically a chromium layer, is deposited on the scatterer film 71 to protect the layers between the sacrificial layer 81 and the silicon wafer top surface 53 from defects and film scratches when the silicon wafer bottom surface 52 is processed.
At step 90, the silicon wafer 51 has been "flipped" so that the silicon wafer bottom surface 52 may be processed and a resist layer 91 has been spun onto the silicon nitride film 61 on the silicon wafer bottom surface 52. Then at step 100, the resist layer 91 has been patterned, such as with an aligner, stepper or electron beam tool, and then developed. At step 110, the silicon nitride layer 61 has been etched down to the silicon wafer bottom surface 52. At step 120, the resist layer 91 has been removed and the silicon wafer 51 has been etched down to the silicon nitride film 61 on the silicon wafer top surface 53. it should be noted that since the silicon wafer 51 has been etched through in step 120, the silicon nitride film 61 on the silicon wafer top surface 53 now becomes a plurality of free standing membranes, and, as such, the remaining process steps occur on membranes only. Next, at step 125, the wafer, which contains a plurality of membranes, has been "flipped" to process the layers on the silicon wafer top surface 53 and the sacrificial layer 81 has been removed leaving the scatterer film 71 forming a "blank mask". At step 140, a second resist layer 141 has been spun on the scatterer film 71 in order to form a pattern on the scatterer film 71. At step 150, the resist is patterned and developed. Then, at step 160, the second resist layer 141 is used as a mask to define the scatterer film 71 and the resist 141 is removed. Thus, at step 160, the mask is completed. Prior art FIG. 2A is an exploded view of the mask at step 160 depicting the patterned scatterer film 71 positioned between "struts" (i.e. patterned silicon nitride film 61 on silicon wafer bottom surface 52 and silicon wafer 51).
Certain problems exist with the mask fabrication methodology shown in prior art FIG. 2. First, this methodology has a long turn around time (TAT). This is due to several factors. One factor is that processing must sequentially be carried out first on one side of the wafer and then on the other side. It is not possible to simultaneously do both. Another factor that produces a long TAT is that additional steps are required using this methodology due to the deposition and removal of protective layers such as in steps 80 and 125 of FIG. 2 that apply and remove the sacrificial layer 81. The additional steps contribute to a long TAT, in addition to higher defects due to additional handling of the silicon wafer and thereby causing a lower yield.
A further problem with the methodology of FIG. 2 is that the mask being formed in FIG. 2 is easily damaged which may reduce the wafer yield. This is because, at steps 140, 150 and 160, all processes must be carried out on very thin (approximately 1,000 .ANG.) membranes, which is very difficult to do and which could easily lead to a broken membrane. Additionally, since the silicon wafer is being processed on both sides, that is the silicon wafer top surface 53 and the back surface 52, care must be taken in handling the wafer so that neither surface is damaged. This results in the use of manual tweezers or an equivalent peripheral device that does not adhere to either side of the silicon wafer that is being processed. As such, the handling of a device undergoing the methodology of FIG. 2 is difficult which may produce a long TAT or low yield. Also, all the problems listed above become even more difficult as the wafer sizes increase and therefore additional membranes may be damaged. A need therefore exists for a mask fabrication methodology that avoids the problems listed above.